The present invention relates generally to integrated circuit (IC) design, and, more particularly, to a voltage boosting circuit design.
As IC geometry keeps shrinking, the supply voltage level also has to be lowered in order to work with small geometric devices. For instance, an older technology with 0.25 μm feature size uses 3.3V supply voltage, but a newer technology, such as those with 65 nm feature size, uses only 1.0V supply voltage. Such kind of low supply voltage creates design complexities as certain circuitry may still require high voltage supplies. For instance, in a Flash memory read operation, a 1.8V needs to be applied to a word-line while a main power supply voltage is 1.0V. In such case, a one-shot boost circuit is typically used to produce the 1.8V voltage from the 1.0V supply voltage. In other applications when power supply voltage has a wide range, for instance, from 1.2V to 1.8V, it is not easy to provide a fixed 1.8V with conventional one-shot boost circuit.
FIG. 1A illustrates a conventional voltage boost circuit 100 comprising a driver 102, a capacitor 106 and a voltage clamping circuit 112. The capacitor 106 is pre-charged. An input voltage at a node IN ramps up to a supply voltage VDD at a time t1. Since the voltage across the capacitor 106 cannot be changed instantly, the voltage at an output node OUT will rise up to a voltage equals to a sum of the VDD and the voltage across the capacitor 106. The voltage level at the output node OUT is controlled by the voltage clamping circuit 112, which is comprised of a certain number of serially connected, forward biased diodes. A forward biased diode provides a voltage drop across its two terminals. The voltage drop is determined by the diode's P-N junction, therefore, is very predictable and near constant.
FIG. 1B shows transient voltage characteristics at the nodes N1 and OUT of the voltage boost circuit 100. The node N1 voltage, V_N1, is driven to VDD at the time t1. The node OUT voltage, V_OUT, has an undesirable spike 122 at the rising edge of the V_OUT. Therefore, the conventional voltage boost circuit 100 has longer setup time. Since the conventional voltage boost circuit 100 clamps voltage by essentially using forward biased diodes to shun current, its power consumption is high. Besides, the clamping voltage level is determined by the P-N junction and may subject to implant variations.
As such, what is desired is a voltage boost circuit that can overcome the aforementioned shortcomings of the conventional voltage boost circuit.